1. Field of the Invention
The present invention relates to a method for driving a semiconductor memory device; and, more particularly, to a method for programming a nonvolatile memory device including one time programmable (OTP) unit cells.
2. Description of Related Art
One time programmable (OTP) unit cells are formed inside a volatile memory device such as Dynamic Random-Access-Memory (DRAM) or a nonvolatile memory device, such as Electrically Erasable Programmable Read-Only-Memory (EEPROM) or flash memory, and are used for memory repair purpose. In addition, OTP unit cells are used for internal operating voltage and frequency trimming in a mixed-signal chip where an analog chip and a digital chip are mixed.
Generally, each OTP unit cell includes an antifuse implemented with a metal-oxide-semiconductor field effect transistor, referred to as a MOS transistor hereafter, and one or more MOS transistors. Such an OTP unit cell is formed inside each memory chip in a single or array configuration and is used for repair or trimming.
FIG. 1 is an equivalent circuit diagram of a typical OTP unit cell.
Referring to FIG. 1, the typical OTP unit cell includes an antifuse ANT_FS and transistors NM1 and NM2. The antifuse ANT_FS is connected between a node B and an input terminal through which a program voltage is inputted. The transistors NM1 and NM2 are n-channel transistors, and are connected in series between the node B and a bit line BL, which is a terminal through which data are outputted during read operation.
FIG. 2 is a block diagram illustrating a memory cell array of a typical nonvolatile memory device.
Referring to FIG. 2, the memory cell array of the typical nonvolatile memory device includes a plurality of unit cells UC arranged in a matrix form. As illustrated in FIG. 1, the unit cell UC includes first and second transistors NM1 and NM2 having n-channels connected in series and one antifuse ANT_FS connected to the first and second transistors NM1 and NM2 in series.
In addition, the memory cell array of the typical nonvolatile memory device includes a plurality of word lines WL0 to WLn, where n is a positive integer herein, configured to select the second transistor NM2 of the unit cell UC. Furthermore, the memory cell array includes a plurality of bit lines BL0 to BLm, where m is a positive integer herein, configured to sense data through a drain of the transistor NM1 to transfer it to a detecting unit (not shown). Moreover, the memory cell array includes a plurality of control lines CL0 to CLn configured to apply a bias voltage to a gate of the first transistor NM1 to thereby control the operation of the first transistor NM1.
Herebelow, description will be made on program and read operations of a conventional nonvolatile memory device.
FIG. 3 is a waveform diagram illustrating a program operation of a conventional nonvolatile memory device.
TABLE 1Operationmode/TerminalACL0 to CLnWL0 to WLnBL0 to BLmProgramVPPHH or LVSSoperationReadVDDHH or LVSSoperation
Program Operation
Referring to Table 1 and FIG. 3, a high voltage VPP is applied to an input terminal A during a programming period TPGM. A first control signal having a first logic level corresponding to a power supply voltage VDD, referred to as logic high level hereafter, is inputted to the control lines CL0 to CLn as a bias voltage. A second control signal of logic high level is inputted to a selected word line of the word lines WL0 to WLn, and the second control signal having a second logic level corresponding to a ground voltage VSS, referred to as logic low level hereafter, is inputted to an unselected word line. The ground voltage VSS is applied to the bit lines BL0 to BLm.
In a selected cell in which a gate dielectric layer of the antifuse is broken down during the program operation, the first and second transistors NM1 and NM2 are turned on in response to the first and second control signals so that the selected bit line and the node B are electrically connected. This allows the ground voltage VSS to be applied to the node B. Accordingly, a high electric field is formed between a substrate and the gate of the antifuse ANT_FS implemented with a MOS transistor, leading to a dielectric breakdown of the gate dielectric layer formed between the gate and the substrate. Thus, the gate of the antifuse ANT_FS and the substrate are electrically shorted.
Read Operation
After the program operation, the power supply voltage VDD is applied to the input terminal A, and the first control signal of logic high level is inputted to the control line CL0 to CLn. The second control signal of logic high level is inputted to a selected word line of the word lines WL0 to WLn, and the second control signal of logic low level is inputted to an unselected word line. The bit lines BL0 to BLm are connected to the detecting unit (not shown). Accordingly, a current path is formed from the input terminal A to the bit line via the antifuse ANT_FS, the first transistor NM1, and the second transistor NM2. Thus, the power supply voltage VDD applied to the input terminal A is transferred to the bit line so that the power supply voltage VDD is detected through the bit line.
However, there are several limitations below in the program operation of the conventional nonvolatile memory device.
As illustrated in FIG. 3, the program operation of the conventional nonvolatile memory device is performed in a static stress manner that the program voltage with a constant level is continuously applied during the programming period TPGM to result in the dielectric breakdown of the gate dielectric layer of the antifuse ANT_FS. In such a static stress manner, electrons are trapped at an interface of the gate dielectric layer of the antifuse ANT_FS, and thus the electric field strength is reduced during the program operation. For this reason, the electric field is not sufficiently applied to the gate dielectric layer of the antifuse during the program operation so that the dielectric breakdown of the gate dielectric layer is not performed normally. Accordingly, a data sensing margin becomes poor to cause a malfunction to occur during the read operation, which degrades the reliability in the read operation of the OTP unit cell.